• Speaker: Ying-Dar Lin (National Chiao Tung University)
• Title: Research Roadmap Driven by Network Benchmarking Lab (NBL): Deep Packet Inspection, Traffic Forensics, Embedded Benchmarking, 4G LTE, and Beyond
• Chair: Satoshi Fujita (Hiroshima University)

Most researchers look for topics from the literature. But my research has been driven mostly by development which in turn has been driven by industrial projects or lab works. We spanned into the areas of cable TV networks, multi-hop cellular, Internet QoS, deep packet inspection, and traffic forensics. Among them, our multi-hop cellular work was the first along this line and has a high impact on both academia and industry, with over 600 citations and standardizations in WLAN mesh (IEEE 802.11s), WiMAX (IEEE 802.16j), Bluetooth (IEEE 802.15.5), and 3GPP LTE-advanced. Side products from our research include a startup (L7 Networks Inc., in 2002), a test lab (Network Benchmarking Lab, NBL, since 2002), and a textbook “Computer Networks: An Open Source Approach” (McGraw-Hill, 2011). It is a perfect time to report my 20-year research as we celebrate the 70th birthday of my Ph.D. thesis advisor, Prof. Mario Gerla. Inspired by his persistent and profound impacts, I think this is merely a half-time report and look forward to another 20 years of research. Keywords: multi-hop cellular, QoS, deep packet inspection, traffic forensics, embedded benchmarking, LTE

• Speaker: Naoaki Yamanaka (Keio University)
• Author: Naoaki Yamanaka, Hidetoshi Takeshita, Satoru Okamoto, Akiko Hirao and Takehiro Sato Keio University, Department of Information and Computer Science, Keio, Japan (YouTube)
• Title: Creating Future Energy Efficient Network Services based on Optical Technologies.
• Chair: Hideharu Amano (Keio University)

Two alternate newly structured optical network architecture is proposed to create new network service. First one is energy efficient, data center centric optical aggregation network based on wavelength/time-slots multiplexing technique. Not only application layer functions but also all layer-3 or upper traffic are transferred through the optical aggregation network and switched at huge centralized router at the data center. Power consumption of the network can be reduce 1/10 – 1/20 compared to the existing Internet. Next is service mash-up network by using broadband optical wire under the IoT generations. All service contents, hardware, and software programs are defined as service parts. Optical wire interconnects some service parts and creates new mash-up service in the network. That crests deep network functionality combining with network and processing functions.

• Speaker: Hirotaka Ono (Kyushu University)
• Title: Recent Advances on Distance Constrained Labeling Problems
• Chair: Satoshi Fujita (Hiroshima University)

Distance constrained labeling problems, e.g, L(p,q)-labeling and (p,q)-total labeling, are originally motivated by the frequency assignment. From the viewpoint of theory, the upper bounds on the labeling numbers and the time complexity of finding a minimum labeling are intensively and extensively studied. In this talk, we survey the recent advances of the distance constrained labeling problems.

• Speaker: Fumihiko Ino (Osaka University)
• Title: The Past, Present, and Future of GPU-Accelerated Grid Computing
• Chair: Koji Nakano (Hiroshima University)

The emergence of compute unified device architecture (CUDA), which relieved application developers from understanding complex graphics pipelines, made the graphics processing unit (GPU) useful not only for graphics applications but also for general applications. In this tutorial, we introduce a cycle sharing system, named GPU grid, which exploits idle GPU cycles for acceleration of scientific applications. Our cycle sharing system implements cooperative multitasking, which is useful to execute guest applications remotely on donated host machines without causing significant slowdown on the host machines. Because our system has been developed since the pre-CUDA era, we also present how our system has been affected by the evolution of GPU architectures.

• Speaker: Hideharu Amano (Keio University)
• Title: Introduction to Interconnection Networks - From System Area Network to Network on Chips -
• Chair: Michihiro Koibuchi (NII)

Interconnection networks connect cabnets in the floors, boards in a cabnet, chips on a board, and modules inside the chip. Since protocols and network structures are not fixed unlike LAN or WAN, there are wide variety on topologies, routing, flow control and media. As an introduction of two other tutorial sessions, typical interconnection networks and techniques around them are explained with recent examples.

• Speaker: Michihiro Koibuchi (NII)
• Title: Future Low-latency Networks for High Performance Computing
• Chair: Hideharu Amano (Keio University)

Interconnection networks are the heart of the high-performance computing systems that include PC clusters and custom massively parallel computers. Their architectural performance factors are topology, routing and switching technique, and their requirements are quite different from those of Internet and local area network. In this tutorial, I consider their trends and research challenges.

• Speaker: Hiroki Matsutani (Keio University)
• Title: Research Challenges on 2-D and 3-D Network-on-Chips
• Chair: Hideharu Amano (Keio University)

The advances in semiconductor technology allow us to integrate a number of processing cores on a single chip or a single package. These many-core processors are expected to boost a wide range of applications from high-performance computing, cyber-physical computing, cloud, and big data processing. This tutorial first introduces recent many-core processors and then focuses on fundamental technologies of 2-D and 3-D Network-on-Chip architectures in terms of network topology, routing algorithm, and router architecture. Recent research challenges on 2-D and 3-D Network-on-Chip architectures, such as 2-D and 3-D wireless technologies, are also surveyed.