Keynote Talks

Speaker: Yasuhiko Nakashima, Nara Institute of Science and Technology

Title: The Road to CGLA — What We Learned and What Comes Next

Abstract The rapid growth of AI and data-intensive computing has created a fundamental challenge: how can we achieve substantially higher energy efficiency without sacrificing the versatility required by diverse applications? While highly specialized accelerators can achieve excellent performance and energy efficiency, their applicability is often limited. In contrast, general-purpose processors provide flexibility but suffer from increasing power consumption and data-movement overheads.

This keynote presents the evolution of the Coarse-Grained Linear Array (CGLA), developed through a long-term exploration of the boundary between general-purpose computing and dedicated accelerators. CGLA, also referred to as CPU-Grounded Linear Array, combines a CPU-like programming model with a highly efficient dataflow-oriented architecture. Its position-independent linear/ring structure avoids the costly placement and routing problems of conventional two-dimensional CGRAs, enabling fast compilation and practical JIT execution. Near-memory processing, broadcast/gather/reuse mechanisms, and continuous coordination with external memory further improve energy efficiency while maintaining programming flexibility.

The talk traces the development from early VLIW and vector processors through LAPP, EMAX, IMAX, and IMAX2, and discusses recent applications including highly quantized LLM inference, sparse computation, scientific computing, image and graph processing, robotics, and security. Prototype systems demonstrate the scalability of CGLA from edge-oriented systems to server and chiplet-based configurations.

Finally, the keynote discusses the next step: building computing infrastructure that can improve energy efficiency by orders of magnitude while preserving as much generality as possible. The road to CGLA is therefore not simply the pursuit of a new accelerator, but an ongoing attempt to reconcile efficiency, programmability, scalability, and sustainability in the post-von-Neumann era.

Speaker: Yuji Shinano, Zuse Institute Berlin

Title: How Should We Exploit Parallelism to Solve Hard Discrete Optimization Problems?

Abstract:

For several decades, the speaker has been developing high-performance solvers for hard discrete optimization problems. Beginning with parallel branch-and-bound algorithms, this work has led to the development of solvers for a wide range of problems, including Mixed-Integer Programming (MIP), the Quadratic Assignment Problem (QAP), the Steiner Tree Problem, and Quadratic Unconstrained Binary Optimization (QUBO).

Over these decades, computing platforms have changed dramatically—from conventional multicore systems to massively parallel architectures and large-scale computing environments. At the same time, optimization solvers themselves have become increasingly sophisticated, making the effective exploitation of parallelism both more important and more challenging.

Drawing on lessons learned from the development of these solvers, this talk revisits a fundamental question: How should we exploit parallelism to solve hard discrete optimization problems? We will examine different forms of parallelism in modern optimization solvers, discuss what has worked—and what has not—in practice, and consider the algorithmic and computational challenges that remain.

Finally, the talk will present the current status of our recent work on parallel MIP solver development and discuss possible directions for the next generation of parallel discrete optimization solvers.